In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability.
In certain charge-domain signal-processing circuits, the charge packets are stored on capacitors. Most charge-domain operations can be described by the well known expression, Q=CV, where Q represents the size of the charge packet, in Coulombs, C represents the capacitance on which the charge packet is stored, in Farads, and V represents the voltage of the node on which the charge packet is stored, in Volts. The process of charge transfer and storage in a charge-domain signal-processing circuit is explained with the aid of FIGS. 1 and 2. These figures omit some of the details needed to implement a complete charge domain signal processing circuit, but they suffice to permit the description below of the essential features of charge storage and transfer in charge-domain circuits (such details are described in other published patent applications by Anthony, M., such as U.S. Patent Publication No. 2007/0279507 entitled “Boosted Charge Transfer Circuit” and U.S. Patent Publication 2008/0205581 entitled “Common-mode Charge Control in a Pipelined Charge-domain Signal-Processing Circuit” hereby incorporated by reference). Charge, as represented by electrons, flows in the opposite direction from conventional current. Note that all descriptions below assume electrons as the signal-charge carriers. The corresponding quantities of charge (Q) in the equations have negative values. The identical description can be applied equally well using holes as charge carriers with reversed voltage polarities.
FIG. 1 depicts a simple charge transfer and storage circuit and FIG. 2 shows the potential charge-storage of node A shown in FIG. 1. Assume Node A has been given an initial voltage of VAic (such as may be imposed by closing a precharge switch PRE at some time prior to time t0). Its potential (voltage) is then allowed to float (such as by then opening switch PRE at time t0). One terminal of capacitor CA, which provides a charge-storage function, is connected to node A; the other terminal of capacitor CA is connected to a static voltage V1. When a quantity of charge (Qi) is transferred onto node A at time t1, (such as by closing switch SW1) the voltage at Node A falls to voltage VA1. Please note that switches SW1 and SW2 are meant to illustrate charge transfer functions at a conceptual level. Practical charge transfer circuits are typically more complex or different, and the exact design of SW1 and SW2 are not pertinent to the present invention. Equation 1 relates the transferred charge, Qi, to the node voltage at A, VA1, given the capacitance of node A, CA, and its initial potential, VAic.VA1=VAic−Qi/CA  Equation 1
In charge storage devices, the allowable voltage at Node A is constrained by various factors relating to the specific circuit implementation. In circuits using electrons as the charge carrier, the initial voltage, VAic, is usually set to the most positive voltage available VA1 is limited by the minimum Voltage (VAmin) at which electrons can be attracted from the transferring source and stored. This constraint sets the maximum allowable charge that can be transferred onto node A. Equation 2 relates the charge capacity of Node A, Qimax1, to the minimum voltage allowed at Node A, VAmin, given the capacitance of node A, CA, and its initial potential VAic.Qimax1=(VAic−VAmin)CA  Equation 2
Charge transfer off of storage node A begins at time t2. At time t2, a switch SW2 is closed which connects node A to a voltage source SV delivering a voltage Vo. The quantity of charge transferred through the voltage source SV is described by Equation 3 which relates the charge transferred through the voltage source, Qo1, to the initial charge transferred to node A, Qi, given the capacitance of node A, CA, its initial potential VAic, and the potential, Vo of the voltage source SV.Qo1=Qi−(VAic−Vo)CA  Equation 3
As stated above, in charge-domain signal-processing circuits, the signal is represented by a charge packet. In this case, the charge Qi transferred onto node A represents the signal, thus the maximum signal value allowed is Qimax1. In all analog circuits, one figure of merit is the signal-to-noise ratio (SNR). Equation 4 describes this quantity.SNR=Signal/Noise=Qimax1/Qnoise  Equation 4
Equation 2 describes the quantity Qimax1. In the simplified circuit of FIG. 1, the quantity Qnoise is often referred to as kTC noise and is proportional to the square root of capacitance, CA. Equation 5 describes this relationship.Qnoise=√(kTCA)  Equation 5
Substituting Equations 5 and 2 into Equation 4 gives Equation 6.SNR=(VAic−VAmin)]√(CA)/√(kT)  Equation 6
From Equation 6, it is clear that SNR is proportional to the square root of CA and the voltage difference (VAic−VAmin). Since a change in either of these quantities will result in a change in Qo1, as expressed in Equation 3, it is not possible to increase SNR without altering the charge transfer characteristics of this simplified circuit. (Similar limitations apply to more complex circuits.) Moreover, the conventional approach of increasing CA to improve SNR can be shown to increase the area occupied by the circuit and also the power consumed. It would therefore be beneficial to improve SNR in some manner that does not create these disadvantages while also not altering the circuit's charge transfer characteristics.